View IS61LV10008-10B_6821856.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 1 rev. 00b 05/15/02 is61lv10008 issi ? copyright ? 2002 integrated silicon solution, inc. all rights reserved. issi reserves the right to make changes to this speci fication and its products at any time without notice. issi assumes no liability arising out of the application or use of any information, products or services desc ribed herein. customers are advised to obtain the latest version of this device specification before relying on any published information and before placing orders fo r products. 1m x 8 high-speed cmos static ram advanced information may 2002 features ? high-speed access times: 8, 10, 12 ns high-performance, low-power cmos process multiple center power and ground pins for greater noise immunity easy memory expansion with ce and oe options ce power-down fully static operation: no clock or refresh required ttl compatible inputs and outputs single 3.3v power supply packages available: ? 48-ball minibga (9mm x 11mm ) ? 36-ball minibga (9mm x 11mm) ? 44-pin tsop (type ii) description the issi is61lv10008 is a very high-speed, low power, 1m-word by 8-bit cmos static ram. the is61lv10008 is fabricated using issi 's high-performance cmos technol- ogy. this highly reliable process coupled with innovative circuit design techniques, yields higher performance and low power consumption devices. when ce is high (deselected), the device assumes a standby mode at which the power dissipation can be reduced down to 250 w (typical) with cmos input levels. the is61lv10008 operates from a single 3.3v power supply and all inputs are ttl-compatible. the is61lv10008 is available in 48 ball mini bga, 36-ball mini bga, and 44-pin tsop (type ii) packages. functional block diagram a0-a19 ce oe we 1m x 8 memory array decoder column i/o control circuit gnd vcc i/o data circuit i/o0-i/o7
2 integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 rev. 00b 05/15/02 is61lv10008 issi ? pin configuration 36 mini bga (b) pin descriptions a0-a19 address inputs ce chip enable input oe output enable input we write enable input i/o0-i/o7 data input / output vcc power gnd ground nc no connection 48-pin mini bga (m ) (9mm x 11mm) 44-pin tsop (type ii ) 1 2 3 4 5 6 a b c d e f g h a0 i/o4 i/o5 gnd vcc i/o6 i/o7 a9 a1 a2 oe a10 nc we a19 a18 ce a11 a3 a4 a5 a17 a16 a12 a6 a7 a15 a13 a8 i/o0 i/o1 vcc gnd i/o2 i/o3 a14 1 2 3 4 5 6 a b c d e f g h nc nc nc gnd vcc nc nc a18 oe nc nc nc nc nc nc a8 a0 a3 a5 a17 nc a14 a12 a9 a1 a4 a6 a7 a16 a15 a13 a10 a2 ce i/o1 i/o3 i/o4 i/o5 we a11 nc i/o0 i/o2 vcc gnd i/o6 i/o7 a19 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 nc nc a0 a1 a2 a3 a4 ce i/o0 i/o1 vcc gnd i/o2 i/o3 we a5 a6 a7 a8 a9 nc nc nc nc nc a18 a17 a16 a15 oe i/o7 i/o6 gnd vcc i/o5 i/o4 a14 a13 a12 a11 a10 a19 nc nc 44 43 42 41
integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 3 rev. 00a 05/15/02 is61lv10008 issi ? absolute maximum ratings (1) symbol parameter value unit v term terminal voltage with respect to gnd ?0.5 to vcc + 0.5 v t bias temperature under bias ?55 to +125 c t stg storage temperature ?65 to +150 c p t power dissipation 1.0 w notes: 1. stress greater than those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect reliability. truth table mode i/o operation vcc current not selected x h x high-z i sb 1 , i sb 2 (power-down) output disabled h l h high-z i cc read h l l d out i cc write l l x d in i cc operating range range ambient temperature v cc commercial 0c to +70c 3.3v +10%, -5% industrial ?40c to +85c 3.3v +10%, -5% capacitance (1,2) symbol parameter cond itions max. unit c in input capacitance v in = 0v 6 pf c i/o input/output capacitance v out = 0v 8 pf notes: 1. tested initially and after any design or process changes that may affect these parameters. 2. test conditions: t a = 25c, f = 1 mhz, vcc = 3.3v.
4 integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 rev. 00b 05/15/02 is61lv10008 issi ? dc electrical characteristics (over operating range) symbol parameter test conditions min. max. unit v oh output high voltage v cc = min., i oh = ?4.0 ma 2.4 ? v v ol output low voltage v cc = min., i ol = 8.0 ma ? 0.4 v v ih input high voltage 2.0 v cc + 0.3 v v il input low voltage (1) ?0.3 0.8 v i li input leakage gnd v in v cc com. ?1 1 a ind. ?5 5 i lo output leakage gnd v out v cc , outputs disabled com. ?1 1 a ind. ?5 5 note: 1. v il = ?3.0v for pulse width less than 10 ns. power supply characteristics (1) (over operating range) -8 -10 -12 symbol parameter test conditions min. max. min. max. min. max. unit i cc vcc dynamic operating v cc = max., com. ? 230 ? 220 ? 210 ma supply current i out = 0 ma, f = f max ind. ? 240 ? 230 ? 220 i sb ttl standby current v cc = max., com. ? 70 ? 60 ? 50 ma (ttl inputs) v in = v ih or v il ind. ? 80 ? 70 ? 60 ce v ih , f = f max . i sb 1 ttl standby current v cc = max., com. ? 50 ? 50 ? 50 ma (ttl inputs) v in = v ih or v il ind. ? 55 ? 55 ? 55 ce v ih , f = 0 i sb 2 cmos standby v cc = max., com. ? 40 ? 40 ? 40 ma current (cmos inputs) ce v cc ? 0.2v, ind. ? 45 ? 45 ? 45 v in v cc ? 0.2v, or v in 0.2v, f = 0 note: 1. at f = f max , address and data inputs are cycling at the maximum frequency, f = 0 means no input lines change.
integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 5 rev. 00a 05/15/02 is61lv10008 issi ? read cycle switching characteristics (1) (over operating range) -8 -10 -12 symbol parameter min. max. min. max. min. max. unit t rc read cycle time 8 ? 10 ? 12 ? ns t aa address access time ? 8 ? 10 ? 12 ns t oha output hold time 3 ? 3 ? 3 ? ns t ace ce access time ? 8 ? 10 ? 12 ns t doe oe access time ? 3.5 ? 4 ? 5 ns t hzoe (2) oe to high-z output ? 3 ? 4 ? 5 ns t lzoe (2) oe to low-z output 0 ? 0 ? 0 ? ns t hzce (2 ce to high-z output ? 3 0 4 0 6 ns t lzce (2) ce to low-z output 3 ? 3 ? 3 ? ns t ba lb , ub access time ? 3.5 ? 4 ? 5 ns t hzb (2) lb , ub to high-z output 0 3 0 3 0 4 ns t lzb (2) lb , ub to low-z output 0 ? 0 ? 0 ? ns t pu power up time 0 ? 0 ? 0 ? ns t pd power down time ? 8 ? 10 ? 12 ns notes: 1. test conditions assume signal transition times of 3 ns or less, timing reference levels of 1.5v, input pulse levels of 0v to 3.0v and output loading specified in figure 1. 2. tested with the load in figure 2. transition is measured 500 mv from steady-stat voltage.
6 integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 rev. 00b 05/15/02 is61lv10008 issi ? ac test loads ac test conditions parameter unit input pulse level 0v to 3.0v input rise and fall times 3 ns input and output timing 1.5v and reference levels output load see figures 1 and 2 figure 1 319 ? 30 pf including jig and scope 353 ? output 3.3v 319 ? 5 pf including jig and scope 353 ? output 3.3v figure 2
integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 7 rev. 00a 05/15/02 is61lv10008 issi ? t rc t oha t aa t doe t lzoe t ace t lzce t hzoe high-z data valid ce_rd2.eps address oe ce d out t hzce read cycle no. 2 (1,3) ( ce and oe controlled) notes: 1. we is high for a read cycle. 2. the device is continuously selected. oe , ce = v il . 3. address is valid prior to or coincident with ce low transitions. ac waveforms read cycle no. 1 (1,2) (address controlled) ( ce = oe = v il ) data valid read1.eps previous data valid t aa t oha t oha t rc d out address
8 integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 rev. 00b 05/15/02 is61lv10008 issi ? write cycle switching characteristics (1,3) (over operating range) -8 -10 -12 symbol parameter min. max. min. max. min. max. unit t wc write cycle time 8 ? 10 ? 12 ? ns t sce ce to write end 6.5 ? 8 ? 9 ? ns t aw address setup time 6.5 ? 8 ? 9 ? ns to write end t ha address hold from write end 0 ? 0 ? 0 ? ns t sa address setup time 0 ? 0 ? 0 ? ns t pwb lb , ub valid to end of write 6.5 ? 8 ? 8 ? ns t pwe 1 we pulse width 6.5 ? 8 ? 8 ? ns t pwe 2 we pulse width ( oe = low) 6.5 ? 10 ? 12 ? ns t sd data setup to write end 4 ? 6 ? 6 ? ns t hd data hold from write end 0 ? 0 ? 0 ? ns t hzwe (2) we low to high-z output ? 3.5 ? 5 ? 6 ns t lzwe (2) we high to low-z output 2 ? 2 ? 2 ? ns notes: 1. test conditions assume signal transition times of 3 ns or less, timing reference levels of 1.5v, input pulse levels of 0v to 3.0v and output loading specified in figure 1. 2. tested with the load in figure 2. transition is measured 500 mv from steady-state voltage. not 100% tested. 3. the internal write time is defined by the overlap of ce low and ub or lb , and we low. all signals must be in valid states to initiate a write, but any one can go inactive to terminate the write. the data input setup and hold timing are referenced t o the rising or falling edge of the signal that terminates the write.
integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 9 rev. 00a 05/15/02 is61lv10008 issi ? ac waveforms write cycle no. 1 (1,2) ( ce controlled, oe = high or low) data undefined t wc valid address t sce t pwe1 t pwe2 t aw t ha high-z t hd t sa t hzwe address ce we d out d in data in valid t lzwe t sd ce_wr1.eps
10 integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 rev. 00b 05/15/02 is61lv10008 issi ? data undefined low t wc valid address t pwe1 t aw t ha high-z t hd t sa t hzwe address ce we d out d in oe data in valid t lzwe t sd ce_wr2.eps notes: 1. the internal write time is defined by the overlap of ce low and we low. all signals must be in valid states to initiate a write, but any one can go inactive to terminate the write. the data input setup and hold timing are referenced to the rising or falling e dge of the signal that terminates the write. 2. i/o will assume the high-z state if oe v ih . ac waveforms write cycle no. 2 (1,2) ( we controlled: oe is high during write cycle)
integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 11 rev. 00a 05/15/02 is61lv10008 issi ? ac waveforms write cycle no. 3 ( we controlled: oe is low during write cycle) data undefined t wc valid address low low t pwe2 t aw t ha high-z t hd t sa t hzwe address ce we d out d in oe data in valid t lzwe t sd ce_wr3.eps
12 integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 rev. 00b 05/15/02 is61lv10008 issi ? ordering information commercial range: 0c to +70c speed (ns) order part no. package 8 is61lv10008-8m 48 mini bga(9mm x 11mm) is61lv10008-8t tsop (type ii) is61lv10008-8b 36 minibga(9mm x 11mm) 10 is61lv10008-10m 48 mini bga(9mm x 11mm) is61lv10008-10t tsop (type ii) IS61LV10008-10B 36 mini bga (9mm x 11mm) 12 is61lv10008-12m 48 mini bga(9mm x 11mm) is61lv10008-12t tsop (type ii) is61lv10008-12b 36 mini bga (9mm x 11mm) industrial range: -40c to +85c speed (ns) order part no. package 8 is61lv10008-8mi 48 mini bga(9mm x 11mm) is61lv10008-8ti tsop (type ii) is61lv10008-8bi 36 minibga(9mm x 11mm) 10 is61lv10008-10mi 48 mini bga(9mm x 11mm) is61lv10008-10ti tsop (type ii) IS61LV10008-10Bi 36 mini bga (9mm x 11mm) 12 is61lv10008-12mi 48 mini bga(9mm x 11mm) is61lv10008-12ti tsop (type ii) is61lv10008-12bi 36 mini bga (9mm x 11mm)

▲Up To Search▲

Price & Availability of IS61LV10008-10B

	To Download IS61LV10008-10B Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .